In general, there has been a tendency to increase the diameter of a wafer in current semiconductor fabrication processes so as to accomplish high integration of a ULSI (ultralarge scale integrated circuit). Also, current semiconductor fabrication has been subjected to more strict standards including the minimum width requirement of 0.13 μm or less. Further, a step of forming a multiple interconnection or multilayer interconnection structure on a wafer is essentially required for improving the quality of a semiconductor device. However, non-planarization of wafer occurring after carrying out one of the above techniques causes many problems, such as a drop in the margin in the subsequent steps or degradation of the quality of a transistor or device. Therefore, planarization processes have been applied to various steps so as to solve such problems.
One of these planarization techniques is CMP (chemical mechanical polishing). During the process of CMP, a wafer surface is pressed against a polishing pad that rotates relative to the surface, and chemically reactive slurry is introduced onto the wafer surface having a pattern, thereby accomplishing planarization of the wafer surface.
Such a CMP technique may be applied to a shallow trench isolation (STI) process, and particularly in a step of polishing an insulating silicon oxide layer 104 until a silicon nitride etch-stop layer 102 is exposed, after depositing the insulating silicon oxide layer 104, so that a trench 103 on a wafer may be embedded therein (see (b) and (c) in FIG. 1). Herein, in order to improve polishing efficiency, selective polishing characteristics between the silicon oxide layer and the silicon nitride layer (the ratio of the polishing rate of the silicon nitride layer to the polishing rate of the silicon oxide layer, hereinafter, referred to as ‘polishing selectivity’) is required to be increased, and also, in order to increase the planarization degree of the whole wafer, the polishing rate of the silicon oxide layer and the polishing rate of the silicon nitride layer are required to be appropriately controlled.
Accordingly, research on control of highly increasing the polishing rate of the silicon oxide layer to the polishing rate of the silicon nitrate layer has been conventionally carried out so as to increase polishing efficiency and to improve planarization of the whole wafer. However, a great deal of such research has been conducted on a chemical method of varying the composition of CMP slurry, while research on improvement of a polishing quality through adjustment of an abrasive's own physical property has been hardly carried out.